The present invention relates generally to an integrated circuit (IC) design, and more particularly to an SRAM device with improved read and write margins.
In deep sub-micron technology, an embedded SRAM, such as an SRAM, has become a very popular storage unit for high-speed communication devices, image processing devices, and other system-on-chip (SOC) products. Two of the most important aspects in designing an SRAM cell are the cell area and the cell stability. The cell area determines about two-thirds of the total chip area of the SRAM, while the cell stability determines the soft-error rate and the tolerance of the memory to variations of the manufacturing process and operating conditions.
A conventional SRAM device is often implemented with a column-based dynamic power supply to provide its memory cells with various levels of supply voltage for read and write operations. This column-based dynamic power supply may cause low read and write margins particularly when the device is operating at a low supply voltage condition. A set of transistor switches along with a logic control circuit used for controlling the switches are requisite to control the power supply for each column of the cells within a memory array. These extra circuits may be larger in physical size, and thus can occupy a large layout area. As the size of SRAM continues to shrink as the technology advances, the read and write margins will be further decreased due to device mismatches and process variations. For example, a process variation may alter the device physics such that the read and write margins may become too narrow to be reasonably practicable.
Desirable in the art of integrated circuit designs are apparatus and methods for increasing the read and write margins for a single-port SRAM device while also reducing the layout area of the device.